International Superconductive Electronics Conference 2007 June 10-14, 2007 Washington, DC, USA

Wednesday Afternoon Oral Session Wednesday, June 13, 14:00-15:50 Oral Session: Digital Circuits: Processor and Memory Chair: TBD Co-Chair: Oleg Mukhanov 14:00-14:30Invited I-S01: Review of the CORE1 Microprocessor Project: Recent Development and Next Plans Nobuyuke Yoshikawa, M. Tanaka, Y. Yamanashi, N. Irie, H. Park, S. Iwasaki K. Taketomi, A. Fujimaki, H.Terai and S. Yorozu 14:30-14:50 O-S01: Half-Nanosecond Latency Measurement on a 64-kbit Josephson-CMOS Memory Kan Fujiwara, Q. Liu, X. Meng, T. Van Duzer, N. Yoshikawa 14:50-15:10 O-S02: Scalable Cache Memory for a Bit-Serial Single-Flux-Quantum Microprocessor N. Irie, M. Tanaka, Y. Yamanashi, H. -J. Park, N. Yoshikawa, H. Terai, S. Yorozu, A. Fujimaki 15:10-15:30 O-S03: Asynchronous High-Speed Operation of RSFQ First-In First-Out Buffers H. Hara, Y. Nobumori, N. Yoshikawa, A. Fujimaki, Y. Hashimoto, H. Terai 15:30-15:50 O-S04: Fast Bit-Serial Multipliers Using RSFQ Logic Circuits H. Park, Y. Yamanashi, K. Taketomi, N. Yoshikawa, A. Fujimaki and N. Takagi